16C6NL Datasheet, PDF (61/70 Pages) Renesas Technology Corp – Renesas MCU

Under development
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M16C/6N Group (M16C/6NL, M16C/6NN)
Memory Expansion Mode and Microprocessor Mode
(For setting with no wait)
Read timing
BCLK
CSi
td(BCLK-CS)
30ns.max
tcyc
th(BCLK-CS)
4ns.min
ADi
BHE
ALE
RD
DBi
td(BCLK-AD)
30ns.max
th(BCLK-AD)
4ns.min
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
td(BCLK-RD)
30ns.max
tac1(RD-DB)
(0.5 ✕ tcyc-60)ns.max
Hi-Z
tSU(DB-RD)
50ns.min
th(BCLK-RD)
0ns.min
th(RD-DB)
0ns.min
Write timing
BCLK
CSi
td(BCLK-CS)
30ns.max
tcyc
th(BCLK-CS)
4ns.min
ADi
BHE
ALE
WR,WRL,
WRH
DBi
td(BCLK-AD)
30ns.max
th(BCLK-AD)
4ns.min
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5 ✕ tcyc-10)ns.min
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
td(BCLK-DB)
40ns.max
Hi-Z
th(BCLK-DB)
4ns.min
tcyc = ¹
f(BCLK)
td(DB-WR)
th(WR-DB)
(0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min
Measuring conditions :
VCC = 3.3 V
Input timing voltage : VIL = 0.6 V, VIH = 2.7 V
Output timing voltage : VOL = 1.65 V, VOH = 1.65 V
Figure 5.14 Timing Diagram (3)
5. Electric Characteristics
VCC = 3.3 V
Rev.2.10 Aug 25, 2006 page 61 of 67
REJ03B0061-0210