16C6NL Datasheet, PDF (38/70 Pages) Renesas Technology Corp – Renesas MCU

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M16C/6N Group (M16C/6NL, M16C/6NN)
5. Electric Characteristics
Timing Requirements
VCC = 5 V
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)
Table 5.11 External Clock Input (XIN Input)
Symbol
Parameter
tC
External clock input cycle time
tw(H)
External clock input HIGH pulse width
tw(L)
External clock input LOW pulse width
tr
External clock rise time
tf
External clock fall time
Table 5.12 Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
tac1(RD-DB) Data input access time (for setting with no wait)
tac2(RD-DB) Data input access time (for setting with wait)
tac3(RD-DB) Data input access time (when accessing multiplexed bus area)
tsu(DB-RD)
Data input setup time
________
tsu(RDY-BCLK) RDY input setup time
__________
tsu(HOLD-BCLK) HOLD input setup time
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
Data input hold time
________
RDY input hold time
__________
HOLD input hold time
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 10⁹ _{– 45 [ns]}
f(BCLK)
Standard
Min.
Max.
Unit
62.5
ns
25
ns
25
ns
15
ns
15
ns
Standard
Min.
Max.
Unit
(NOTE 1) ns
(NOTE 2) ns
(NOTE 3) ns
40
ns
30
ns
40
ns
0
ns
0
ns
0
ns
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 10⁹
– 45 [ns]
f(BCLK)
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 10⁹
– 45 [ns]
f(BCLK)
n is “2” for 2-wait setting, “3” for 3-wait setting.
Rev.2.10 Aug 25, 2006 page 38 of 67
REJ03B0061-0210