PD16754_15 Datasheet, PDF (6/21 Pages) Renesas Technology Corp – 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES)

µPD16754
4. PIN FUNCTIONS
(1/2)
Pin Symbol
S1 to S384
D00 to D07
D10 to D17
D20 to D27
D30 to D37
D40 to D47
D50 to D57
R,/L
STHR
STHL
Pin Name
Driver
Display data
I/O
Description
Output The D/A converted 256-gray-scale analog voltage is output.
Input The display data is input with a width of 48 bits, viz., the gray scale data (8 bits)
by 6 dots (2 pixels).
DX0: LSB, DX7: MSB
Shift direction control
Right shift start pulse
Left shift start pulse
Input
I/O
I/O
These refer to the start pulse input/output pins when driver ICs are connected
in cascade. The shift directions of the shift registers are as follows.
R,/L = H: STHR input, S1 → S384, STHL output
R,/L = L: STHL input, S384 → S1, STHR output
These refer to the start pulse I/O pins when driver ICs are connected in
cascade. Fetching of display data starts when H is read at the rising edge of
CLK.
R,/L = H (right shift): STHR input, STHL output
R,/L = L (left shift): STHL input, STHR output
A high level should be input as the pulse of one cycle of the clock signal.
If the start pulse input is more then 2CLK, the first 1CLK of the high-level input
is valid.
CLK
Shift clock
STB
POL
Latch
Polarity
POL21,
POL22
Data inversion
TEST
TEST
Input
Input
Input
Input
Input
Refers to the shift register’s shift clock input. At the rising edge of the 64th
after the start pulse input, the start pulse output reaches the high level, thus
becoming the start pulse of the next-level driver. If 66th clock pulses are input
after input of the start pulse, input of display data is halted automatically. The
contents of the shift register are cleared at the STB’s rising edge.
The contents of the data register are transferred to the latch circuit at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the driver.
It is necessary to ensure input of one pulse per horizontal period.
POL = L: The S2n− 1 output uses V0 to V7 as the reference supply. The S2n
output uses V8 to V15 as the reference supply.
POL = H: The S2n−1 output uses V8 to V15 as the reference supply. The S2n
output uses V0 to V7 as the reference supply.
S2n−1 indicates the odd output: and S2n indicates the even output. Input of the
POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising
edge.
Data inversion can invert when display data is loaded.
POL21: Invert/not invert of display data D00 to D07, D10 to D17, D20 to D27.
POL22: Invert/not invert of display data D30 to D37, D40 to D47, D50 to D57.
POL21, POL22 = H: Data inversion loads display data after inverting it.
POL21, POL22 = L: Data inversion does not invert input data.
When this function is required, leave this pin = H or open.
TEST is pulled up to the VDD1 power supply inside the IC.
4
Data Sheet S16434EJ1V0DS