PD16754_15 Datasheet, PDF (17/21 Pages) Renesas Technology Corp – 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES)

µPD16754
Timing Requirement (TA = −10 to +75°C, VDD1 = 3.0 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Clock Pulse Width
PWCLK
25
Clock Pulse High Period
PWCLK(H)
4
Clock Pulse Low Period
PWCLK(L)
4
Data Setup Time
tSETUP1
2
Data Hold Time
tHOLD1
2
Start Pulse Setup Time
tSETUP2
2
Start Pulse Hold Time
tHOLD2
2
POL21, POL22 Setup Time
tSETUP3
2
POL21, POL22 Hold Time
tHOLD3
2
STB Pulse Width
PWSTB
2
Last Data Timing
tLDT
2
CLK-STB Time
tCLK-STB
CLK ↑ → STB ↑
6
STB-CLK Time
tSTB-CLK
STB ↑ → CLK ↑
6
Time Between STB and Start Pulse tSTB-STH
STB ↑ → STHR (STHL) ↑
2
POL-STB Time
tPOL-STB
POL ↑ or ↓ → STB ↑
–5
STB-POL Time
tSTB-POL
STB ↓ → POL ↓ or ↑
6
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
CLK
ns
ns
CLK
ns
ns
Data Sheet S16434EJ1V0DS
15