PD16753_15 Datasheet, PDF (6/22 Pages) Renesas Technology Corp – 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES)

µ PD16753
4. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
I/O
Description
S1 to S384
Driver output
O The D/A converted 256-gray-scale analog voltage is output.
D00 to D07
D10 to D17
D20 to D27
Display data input
I The display data is input with a width of 48 bits, viz., the gray scale data (8 bits)
by 6 dots (2 pixels).
DX0: LSB, DX7: MSB
D30 to D37
D40 to D47
D50 to D57
R,/L
Shift direction control
I These refer to the start pulse input/output pins when driver ICs are connected
input
in cascade. The shift directions of the shift registers are as follows.
R,/L = H: STHR input, S1 → S384, STHL output
R,/L = L: STHL input, S384 → S1, STHR output
STHR
Right shift start pulse I/O These refer to the start pulse I/O pins when driver ICs are connected in
input/output
cascade. Fetching of display data starts when H is read at the rising edge of
CLK.
STHL
Left shift start pulse
input/output
I/O ^{R,/L = H (right shift): STHR input, STHL output}
R,/L = L (left shift): STHL input, STHR output
A high level should be input as the pulse of one cycle of the clock signal.
If the start pulse input is more then 2CLK, the first 1CLK of the high-level input
is valid
CLK
STB
POL
POL21
POL22
LPC
Shift clock input
Latch input
Polarity input
Data inversion input
Low power control
input
I Refers to the shift register’s shift clock input. At the rising edge ot the 64th
after the start pulse input, the start pulse output reaches the hight level, thus
becoming the start pulse of the next-level driver. If 66th clock pulses are input
after input of the start pulse, input of display data is halted automatically. The
contentsu of the shift register are cleared at the STB’s rising edge.
I The contents of the data register are transferred to the latch circuit at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the driver.
It is necessary to ensure input of one pulse per horizontal period.
I
POL = L: The S2n–1 output uses V0 to V7 as the reference supply. The S2n
output uses V8 to V15 as the reference supply.
POL = H: The S2n–1 output uses V8 to V15 as the reference supply. The S2n
output uses V0 to V7 as the reference supply.
S2n-1 indicates the odd output: and S2n indicates the even output. Input of the
POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising
edge.
I Data inversion can invert when display data is loaded.
POL21: Invert/not invert of display data D00 to D07, D10 to D17, D20 to D27.
POL22: Invert/not invert of display data D30 to D37, D40 to D47, D50 to D57.
POL21/22 = H: Data inversion loads display data after inverting it.
POL21/22 = L: Data inversion does not invert input data.
I
The current consumption of VDD2 is lowered by controlling the constant current
source of the output amplifier. This pin is pulled up to the VDD1 power supply
inside the IC.
LPC = L: Normal power mode
LPC = H or Open: Low power mode (the static current consumption of VDD2
reduced to about 2/3 of the normal current consumption.)
4
Data Sheet S15630EJ1V0DS