PD16753_15 Datasheet, PDF (13/22 Pages) Renesas Technology Corp – 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES)

8. RELATIONSHIP BETWEEN STB, CLK, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
Figure 8−1. Output Circuit Block Diagram
µ PD16753
DAC
Output AMP
−
+
SW1
Sn (Vx)
SW1 switches according to the level of STB signal.
STB = L: SW = ON
STB = H: SW = OFF
Figure 8−2. Output Circuit Timing Chart
CLK
STB
Sn (VX)
[1]
[1']
tSTB-CLK
SW1: OFF
Hi-Z
STB = H is loaded with the rising edge of CLK [1]. However, when not satisfying the specification of tSTB-CLK, STB =
H is loaded with the rising edge of the next CLK [1’]. Latch operation of display data is completed with the falling
edge of the next CLK which loaded STB = H. Therefore, in order to complete latch operation of display data, it is
necessary to input at least 2 CLK in STB = H period.
Data Sheet S15630EJ1V0DS
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