English
Language : 

M37735S4LHP Datasheet, PDF (6/37 Pages) Mitsubishi Electric Semiconductor – 16-BIT CMOS MICROCOMPUTER
New product
MITSUBISHI MICROCOMPUTERS
M37735S4LHP
16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37735S4LHP has the same functions as the M37735MHBXXXFP
except for the following:
(1) The memory map is different.
(2) The processor mode is different.
(3) The reset circuit is different.
(4) Pulse output port mode of timer A is available.
(5) The function of ROM area modification is not available.
Refer to the section on the M37735MHBXXXFP, except for above
(1)–(5).
MEMORY
The memory map is shown in Figure 1. The address space has a
capacity of 16 Mbytes and is allocated to addresses from 016 to
FFFFFF16. The address space is divided by 64-Kbyte unit called bank.
The banks are numbered from 016 to FF16.
However, banks 1016–FF16 of the M37735S4LHP cannot be
accessed.
Built-in RAM and control registers for internal peripheral devices are
assigned to bank 016.
Addresses FFD616 to FFFF16 are the RESET and interrupt vector
addresses and contain the interrupt vectors. Use ROM for memory
of this address.
The 2048-byte area allocated to addresses from 8016 to 87F16 is the
built-in RAM. In addition to storing data, the RAM is used as stack
during a subroutine call or interrupts.
Peripheral devices such as I/O ports, A-D converter, serial I/O, timer,
and interrupt control registers are allocated to addresses from 016 to
7F16.
A 256-byte direct page area can be allocated anywhere in bank 016
by using the direct page register (DPR). In the direct page addressing
mode, the memory in the direct page area can be accessed with two
words. Hence program steps can be reduced.
Bank 016
Bank 116
00000016
00FFFF16
01000016
01FFFF16
00000016
00007F16
00008016
Internal RAM
2048 bytes
00087F16
Bank FE16
FE000016
Bank FF16
FEFFFF16
FF000016
FFFFFF16
00FFD616
00FFFF16
Fig. 1 Memory map
: Internal
: External
Note. Banks 1016–FF16 cannot be accessed in the M37735S4LHP.
00000016
Internal peripheral
devices
control registers
refer to Fig. 2 for
detail information
00007F16
Interrupt vector table
00FFD616 A-D/UART2 trans./rece.
UART1 transmission
UART1 receive
UART0 transmission
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2/Key input
INT1
INT0
Watchdog timer
DBC
BRK instruction
00FFFE16
Zero divide
RESET
5