M37735S4LHP Datasheet, PDF (14/37 Pages) Mitsubishi Electric Semiconductor – 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37735S4LHP
16-BIT CMOS MICROCOMPUTER
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CS0 to CS4 are the chip select signals and are “L” when the address
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shown in Table 2 is accessed. RSMP is the ready-sampling signal
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which is output for the RDY input described later when the external
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memory area is accessed. By inputting logical AND of RSMP and
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CSn (n = 0 to 4) to the RDY pin, read/write term for any address areas
can be extended by 1 cycle of clock 1. In addition, the read/write
term can also be extended by 2 cycles of clock 1 if the above
function and wait 0/1 function specified with the wait bit are used
together.
Pins P10/A8/D8 — P17/A15/D15 have two functions depending on the
level of the BYTE pin.
When the BYTE pin level is “L”, pins P10/A8/D8 — P17/A15/D15 function
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as address (A8 to A15) output pins while RDE or WEL, WEH are “H”
and as odd address data I/O pins while these signals are “L”. However,
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if an internal memory is read, external data is ignored while RDE is
“L”.
When the BYTE pin level is “H”, pins P10/A8/D8 — P17/A15/D15 function
as address (A8 to A15) output pins.
Pins P20/A0/D0 — P27/A7/D7 have two functions depending on the
level of the BYTE pin.
When the BYTE pin level is “L”, pins P20/A0/D0 — P27/A7/D7 function
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as address (A0 to A7) output pins while RDE or WEL, WEH are “H” and
as even address data I/O pins while these signals are “L”. However,
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if an internal memory is read, external data is ignored while RDE is
“L”.
When the BYTE pin level is “H”, pins P20/A0/D0 — P27/A7/D7 function
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as address (A0 to A7) output pins while RDE or WEL, WEH are “H” and
as even and odd address data I/O pins while these signals are “L”.
However, if an internal memory is read, external data is ignored while
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RDE is “L”.
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WEL, WEH are the write-enable low signal and the write-enable high
signal, respectively. These signals are “L” during the data write term
of the write cycle, but their operations differ depending on the BYTE
pin level.
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In the case the BYTE pin level is “L”, WEL is “L” when writing to
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an even address, WEH is “L” when writing to an odd address, and
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both WEL and WEH are “L” when writing to even and odd addresses.
In the case the BYTE pin level is “H”, regardless of address, only
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WEL is “L”, and WEH retains “H”. WEL and WEH can also be fixed to
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“H” when the internal memory is accessed, same as RDE, by writing
“1” to the signal output disable selection bit.
ALE is an address latch enable signal used to latch the address signal
from a multiplexed signal of address and data. The latch is transparent
while ALE is “H” to let the address signal pass through and held
while ALE is “L”.
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HLDA is a hold acknowledge signal and is used to notify externally
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when the microcomputer receives HOLD input and enters into hold
state.
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HOLD is a hold request signal. It is an input signal used to put the
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microcomputer in hold state. HOLD input is accepted when the internal
clock falls from “H” level to “L” level while the bus is not used.
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Pins P00/CS0 — P31/WEH and RDE are floating while the microcomputer
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stays in hold state. After HLDA signal changes to “L” level and one
cycle of internal clock passed, these ports become floating. After
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HLDA signal changes to “H” level and one cycle of internal clock
passed, these ports are released from floating state.
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RDY is a ready signal. If this signal goes “L”, the internal clock
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stops at “L”. RDY is used when slow external memory is attached.
P42/ 1 pin is an output pin for clock 1. The 1 output is
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independent of RDY and does not stop even when internal clock
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stops because of “L” input to the RDY pin.
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