HD74CDCV857 Datasheet, PDF (6/13 Pages) Hitachi Semiconductor – 2.5-V Phase-lock Loop Clock Driver

HD74CDCV857
Recommended Operating Conditions
Item
Symbol Min
Typ
Max
Unit Conditions
Supply voltage
Output supply voltage
DC input signal voltage ^*1
High level input voltage
Low level input voltage
Differential input signal voltage
Differential cross point voltage ^*2
Output current
Input slew rate
AV_CC
V_DDQ
V_IHG
V_ILG
V_ID
V_IX
V_OX ^*3
I_OH
I_OL
SR
2.3
2.5
2.3
2.5
–0.3
—
1.7
—
–0.3
—
0.36
—
0.5×V_DDQ —
–0.20
—
—
—
—
1
—
2.7
V
2.7
V
V_DDQ+0.3 V
V_DDQ+0.3 V
0.7
V
All pins
PWRDWN input pin
PWRDWN input pin
V_DDQ+0.6 V
0.5×V_DDQ V
+0.20
–12
mA
12
4
V/ns 20% – 80%
Operating temperature
T_a
0
—
70
°C
Notes:
Inputs pins must be prevent from floating.
Feedback inputs (FBIN, FBIN) may float when the device is in low power mode.
1. DC input signal voltage specifies the allowable dc execution of differential input.
2. Differential cross point voltage is expected to track variations of V_DDQ and is the voltage at which
the differential signals must be crossing. (See figure1)
3. Guaranteed by design, not 100% tested in production.
CLK
V_ID
CLK
Crossing point
Figure 1 Differential input levels
Rev.7.00, Oct.09.2003, page 6 of 12