HD74CDCV857 Datasheet, PDF (1/13 Pages) Hitachi Semiconductor – 2.5-V Phase-lock Loop Clock Driver

HD74CDCV857
2.5-V Phase-lock Loop Clock Driver
Description
REJ03D0135–0700Z
(Previous ADE-205-335E (Z))
Preliminary
Rev.7.00
Oct.09.2003
The HD74CDCV857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is
specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.
Features
• DDR266 / PC2100-Compliant
• Supports 60 MHz to 170 MHz operation range
• Distributes one differential clock input pair to ten differential clock outputs pairs
• Supports spread spectrum clock requirements meeting the PC100 SDRAM registered DIMM
specification
• External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input
• Supports 2.5V analog supply voltage (AV_CC), and 2.5 V V_DDQ
• No external RC network required
• Sleep mode detection
• 48pin TSSOP (Thin Shrink Small Outline Package)
Function Table
Inputs
: Outputs
AV_CC PWRDWN CLK CLK : Y
Y
GND H
L
H
:L
H
GND H
H
L
:H
L
X
L
L
H
:Z
Z
X
L
H
L
:Z
Z
2.5 V H
L
H
:H
L
2.5 V H
H
L
:H
L
2.5 V X
0 MHz 0 MHz : Z
Z
H:
L:
X:
Z:
Note:
High level
Low level
Don’t care
High impedance
1. Bypasse mode is used for RENESAS test mode.
FBOUT
L
H
Z
Z
H
H
Z
FBOUT ^:
H
:
L
:
Z
:
Z
:
L
:
L
:
Z
:
PLL
Bypassed / off ^*1
Bypassed / off ^*1
off
off
on
on
off
Rev.7.00, Oct.09.2003, page 1 of 12