R8C32A Datasheet, PDF (591/603 Pages) Renesas Technology Corp – MCU M16C FAMILY / R8C/Tiny SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/32A Group
33. Usage Notes
33.16 Notes on Flash Memory
33.16.1 CPU Rewrite Mode
33.16.1.1 Prohibited Instructions
The following instructions cannot be used while the program ROM area is being rewritten in EW0 mode
because they reference data in the flash memory: UND, INTO, and BRK.
33.16.1.2 Non-Maskable Interrupts
Tables 33.1 and 33.2 show CPU Rewrite Mode Interrupts (1) and (2), respectively.
Table 33.1 CPU Rewrite Mode Interrupts (1)
Mode
EW0
EW1
Erase/
Write
Target
Data
flash
Status
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
or FMR22 = 0)
During
auto-programming
Program During auto-erasure
ROM (suspend enabled)
During auto-erasure
(suspend disabled)
During
auto-programming
Data
flash
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
or FMR22 = 0)
During
auto-programming
Program During auto-erasure
ROM (suspend enabled)
Maskable Interrupt
• Address Match
• Address Break
(Note 1)
When an interrupt request is acknowledged, interrupt handling is executed.
If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request),
the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory
suspends auto-erasure after td(SR-SUS).
If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request
disabled by interrupt request), set the FMR 21 bit to 1 during interrupt handling. The flash
memory suspends auto-erasure after td(SR-SUS).
While auto-erasure is being suspended, any block other than the block during auto-
erasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit
to 0 (erase restart).
Interrupt handling is executed while auto-erasure or auto-programming is being
performed.
Usable by allocating a vector in RAM.
Not usable during auto-erasure or
auto-programming.
When an interrupt request is acknowledged, interrupt handling is executed.
If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory
suspends auto-erasure after td(SR-SUS).
If erase-suspend is required while the FMR22 bit is set to 0, set the FMR 21 bit to 1 during
interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS).
While auto-erasure is being suspended, any block other than the block during auto-
erasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit
to 0.
Interrupt handling is executed while auto-erasure or auto-programming is being
performed.
Auto-erasure suspends after td(SR-SUS) and interrupt handling is executed. Auto-
erasure can be restarted by setting the FMR21 bit to 0 after interrupt handling completes.
While auto-erasure is being suspended, any block other than the block during auto-
erasure execution can be read.
During auto-erasure Auto-erasure and auto-programming have priority and interrupt requests are put on
(suspend disabled standby. Interrupt handling is executed after auto-erase and auto-program complete.
or FMR22 = 0)
During
auto-programming
FMR21, FMR22: Bits in FMR2 register
Note:
1. Do not use a non-maskable interrupt while block 0 is being auto-erased because the fixed vector is allocated in block 0.
REJ09B0458-0010 Rev.0.10 Apr 01, 2008
Page 563 of 572