R8C32A Datasheet, PDF (257/603 Pages) Renesas Technology Corp – MCU M16C FAMILY / R8C/Tiny SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
19.2.10 Timer RC Control Register 2 (TRCCR2)
Address 0130h
Bit b7
b6
b5
b4
Symbol TCEG1 TCEG0 CSTP
—
After Reset 0
0
0
1
b3
b2
—
POLD
1
0
b1
POLC
0
b0
POLB
0
Bit Symbol
Bit Name
Function
R/W
b0 POLB PWM mode output level control 0: TRCIOB output level selected as “L” active
R/W
bit B ⁽¹⁾
1: TRCIOB output level selected as “H” active
b1 POLC PWM mode output level control 0: TRCIOC output level selected as “L” active
R/W
bit C ⁽¹⁾
1: TRCIOC output level selected as “H” active
b2 POLD PWM mode output level control 0: TRCIOD output level selected as “L” active
R/W
bit D ⁽¹⁾
1: TRCIOD output level selected as “H” active
b3
— Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
b4
—
b5 CSTP _{TRC count operation select bit} ⁽²⁾ 0: Count continues at compare match with the
R/W
TRCGRA register
1: Count stops at compare match with the TRCGRA
register
b6 TCEG0 _{TRCTRG input edge select bit} ^{(3) b7 b6}
R/W
b7 TCEG1
0 0: Disable the trigger input from the TRCTRG pin _R/W
0 1: Rising edge selected
1 0: Falling edge selected
1 1: Both edges selected
Notes:
1. Enabled when in PWM mode.
2. For notes on PWM2 mode, refer to 19.9.6 TRCMR Register in PWM2 Mode.
3. In timer mode and PWM mode these bits are disabled.
19.2.11 Timer RC Digital Filter Function Select Register (TRCDF)
Address 0131h
Bit b7
b6
b5
b4
b3
b2
b1
b0
Symbol DFCK1 DFCK0 — DFTRG DFD
DFC
DFB
DFA
After Reset 0
0
0
0
0
0
0
0
Bit Symbol
Bit Name
Function
R/W
b0
DFA _{TRCIOA pin digital filter function select bit} ⁽¹⁾ 0: Function is not used
R/W
b1
DFB _{TRCIOB pin digital filter function select bit} ^{(1) 1: Function is used}
R/W
b2
DFC _{TRCIOC pin digital filter function select bit} ⁽¹⁾
R/W
b3
DFD _{TRCIOD pin digital filter function select bit} ⁽¹⁾
R/W
b4 DFTRG _{TRCTRG pin digital filter function select bit} ⁽²⁾
R/W
b5
— Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
b6 DFCK0 _{Clock select bits for digital filter function} ^{(1, 2) b7 b6}
b7 DFCK1
0 0: f32
0 1: f8
R/W
R/W
1 0: f1
1 1: Count source (clock selected by bits
TCK2 to TCK0 in the TRCCR1
register)
Notes:
1. These bits are enabled for the input capture function.
2. These bits are enabled when in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b,
10b, or 11b (TRCTRG trigger input enabled).
REJ09B0458-0010 Rev.0.10 Apr 01, 2008
Page 229 of 572