R8C32A Datasheet, PDF (282/603 Pages) Renesas Technology Corp – MCU M16C FAMILY / R8C/Tiny SERIES

Under development ^{Preliminary specification}
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
19.6.1 Timer RC Control Register 1 (TRCCR1) in PWM Mode
Address 0121h
Bit b7
Symbol CCLR
After Reset 0
b6
TCK2
0
b5
TCK1
0
b4
TCK0
0
b3
TOD
0
b2
TOC
0
b1
TOB
0
b0
TOA
0
Bit Symbol
Bit Name
Function
R/W
b0
TOA _{TRCIOA output level select bit} ⁽¹⁾ Disabled in PWM mode
R/W
b1
TOB _{TRCIOB output level select bit} ^{(1, 2)} 0: Initial output selected as non-active level
R/W
b2
TOC _{TRCIOC output level select bit} ^{(1, 2) 1: Initial output selected as active level}
R/W
b3
TOD _{TRCIOD output level select bit} ^{(1, 2)}
R/W
b4 TCK0 _{Count source select bit} ⁽¹⁾
b5 TCK1
b6 TCK2
b6 b5 b4
0 0 0: f1
0 0 1: f2
0 1 0: f4
R/W
R/W
R/W
0 1 1: f8
1 0 0: f32
1 0 1: TRCCLK input rising edge
1 1 0: fOCO40M
1 1 1: fOCO-F ⁽³⁾
b7 CCLR TRC counter clear select bit
0: Disable clear (free-running operation)
R/W
1: Clear by compare match in the TRCGRA register
j = B, C or D
Notes:
1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the
TRCCR1 register is set.
3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.
19.6.2 Timer RC Control Register 2 (TRCCR2)
Address 0130h
Bit b7
b6
b5
b4
Symbol TCEG1 TCEG0 CSTP
—
After Reset 0
0
0
1
b3
b2
—
POLD
1
0
b1
POLC
0
b0
POLB
0
Bit Symbol
Bit Name
Function
R/W
b0 POLB PWM mode output level control 0: TRCIOB output level selected as “L” active
R/W
bit B ⁽¹⁾
1: TRCIOB output level selected as “H” active
b1 POLC PWM mode output level control 0: TRCIOC output level selected as “L” active
R/W
bit C ⁽¹⁾
1: TRCIOC output level selected as “H” active
b2 POLD PWM mode output level control 0: TRCIOD output level selected as “L” active
R/W
bit D ⁽¹⁾
1: TRCIOD output level selected as “H” active
b3
— Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
b4
—
b5 CSTP _{TRC count operation select bit} ⁽²⁾ 0: Count continues at compare match with the
R/W
TRCGRA register
1: Count stops at compare match with the TRCGRA
register
b6 TCEG0 _{TRCTRG input edge select bit} ^{(3) b7 b6}
R/W
b7 TCEG1
0 0: Disable the trigger input from the TRCTRG pin
0 1: Rising edge selected
R/W
1 0: Falling edge selected
1 1: Both edges selected
Notes:
1. Enabled when in PWM mode.
2. For notes on PWM2 mode, refer to 19.9.6 TRCMR Register in PWM2 Mode.
3. In timer mode and PWM mode these bits are disabled.
REJ09B0458-0010 Rev.0.10 Apr 01, 2008
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