M16C5LD_15 Datasheet, PDF (59/88 Pages) Renesas Technology Corp – RENESAS MCU

M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
5.1.2 Recommended Operating Conditions
Table 5.2 Operating Conditions (1)
V_CC = 2.7 V to 5.5 V, T_opr = -40°C to 85°C unless otherwise specified.
Symbol
Characteristic
V_CC
AV_CC
V_SS
AV_SS
V_IH
V_IL
I_OH(sum)
I_OH(peak)
I_OH(avg)
I_OL(sum)
I_OL(peak)
I_OL(avg)
f_(XIN)
f_(XCIN)
f_(PLL)
f_(BCLK)
t_su(PLL)
Supply voltage
Analog supply voltage
Ground voltage
Analog ground voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
P9_7, P10_0 to P10_7
High level
input voltage ^{XIN, RESET, CNVSS}
SDAMM, SCLMM
When I²C-bus input level selected
When SMBUS input level selected
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
P9_7, P10_0 to P10_7
Low level
input voltage ^{XIN, RESET, CNVSS}
SDAMM, SCLMM
When I²C-bus input level selected
When SMBUS input level selected
High peak
output
current
Sum of I_OH(peak) at P0_0 to P0_7, P1_0 to P1_7, P2_0 to
P2_7, P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to
P8_7, P9_0 to P9_3, P9_5 to P9_7, P10_0 to P10_7
High level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
peak output to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
current
P9_7, P10_0 to P10_7
High level
average
output
current ⁽¹⁾
Low peak
output
current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
P9_7, P10_0 to P10_7
Sum of I_OL(peak) atP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0
to P9_3, P9_5 to P9_7, P10_0 to P10_7
Low level P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
peak output to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
current
P9_7, P10_0 to P10_7
Low level
average
output
current ⁽¹⁾
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P6_0
to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_3, P9_5 to
P9_7, P10_0 to P10_7
Main clock input oscillation frequency ⁽²⁾
Sub clock oscillation frequency
PLL clock oscillation frequency ⁽²⁾
VCC = 2.7 V to 5.5 V
VCC = 3.0 V to 5.5 V
CPU operation frequency
Wait time to stabilize PLL frequency
synthesizer
VCC = 5.0 V
VCC = 3.0 V
Standard
Min.
Typ.
Max.
2.7
5.5
V_CC
0
0
0.7 V_CC
V_CC
0.8 V_CC
0.7 V_CC
2.1
V_CC
V_CC
V_CC
0
0.3 V_CC
0
0.2 V_CC
0
0.3 V_CC
0
0.8
-80.0
-10.0
-5.0
80.0
10.0
5.0
2
20
32.768
50
10
25
10
32
2
32
2
3
Unit
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
MHz
kHz
MHz
MHz
ms
Notes:
1. The mean output current is the mean value within 100 ms.
2. Refer to Figure 5.1 “Main Clock Input Oscillation Frequency, PLL Clock Oscillation Frequency” for the relationship between
main clock oscillation frequency/PLL clock oscillation frequency and supply voltage.
R01DS0132EJ0120 Rev.1.20
Nov 25, 2011
Page 59 of 84