H8S20103 Datasheet, PDF (586/992 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/Tiny Series

Section 16 Timer RD
TRDCNT value
GRA_0
GRB_0
GRA_1
GRB_1
H'0000
FTIOB0
FTIOD0
Counter cleared by GRA compare match
Time
FTIOA1
FTIOC1
FTIOB1
FTIOD1
FTIOC0
Figure 16.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0)
In reset synchronous PWM mode, TRDCNT_0 and TRDCNT_1 perform increment and
independent operations, respectively. However, GRA_1 and GRB_1 are separated from
TRDCNT_1. When a compare match occurs between TRDCNT_0 and GRA_0, a counter is
cleared and an increment operation is restarted from H'0000.
The PWM pin outputs 0 or 1 whenever a compare match between GRB_0, GRA_1, GRB_1 and
TRDCNT_0 or counter clearing occur.
For details on operations when reset synchronous PWM mode and buffer operation are
simultaneously set, see section 16.3.9, Buffer Operation.
Rev. 1.00 Oct. 03, 2008 Page 560 of 962
REJ09B0465-0100