H8S20103 Datasheet, PDF (431/992 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/Tiny Series

Section 13 Timer RA
13.2.5 Timer RA Prescaler Register (TRAPRE)
Address: H'FF06F3
Bit:
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
TRAPRE consists of a reload register and an 8-bit counter, each with an initial value of H'FF.
If a down-count is performed using the count source selected with TRAMR and an underflow
occurs, the value of the reload register is loaded to the counter. The underflow becomes a count
source for TRATR.
The reload register and the counter are assigned to the same address. On write, a value is written
to the reload register, and on read, a counter value is read. During a write to TRAPRE the load
timing from the reload register to the counter differs between counting in progress and counting
stopped. Writing to TRAPRE when counting is stopped causes the data to be written to both the
reload register and the counter. Writing to TRAPRE during counting causes the new value to be
written to the reload register after four cycles of count source, and to be loaded to the counter in
synchronization with the next count source.
Rev. 1.00 Oct. 03, 2008 Page 405 of 962
REJ09B0465-0100