H8S20103 Datasheet, PDF (346/992 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/Tiny Series

Section 10 I/O Ports
10.8.11 Port Data Register A (PDRA)
Address: H'FFFFE9
Bit:
b7
PDRA7
Value after reset:
0
b6
PDRA6
0
b5
PDRA5
0
b4
PDRA4
0
b3
PDRA3
0
b2
PDRA2
0
b1
PDRA1
0
b0
PDRA0
0
Bit Symbol
7 PDRA7
6 PDRA6
5 PDRA5
4 PDRA4
3 PDRA3
2 PDRA2
1 PDRA1
0 PDRA0
Bit Name
Port A7 data
Port A6 data
Port A5 data
Port A4 data
Port A3 data
Port A2 data
Port A1 data
Port A0 data
Description
R/W
0: Low level
R/W
1: High level
R/W
PDRA is a register that stores output data for port A R/W
pins. When PCRA bits are set to 1, the values
stored in PDRA are output.
R/W
When PDRA is read while PCRA bits are set to 1, ^R/W
the values stored in PDRA are read. If PDRA is R/W
read while PCRA bits are cleared to 0, the pin
R/W
states are read regardless of the value stored in
PDRA.
R/W
Rev. 1.00 Oct. 03, 2008 Page 320 of 962
REJ09B0465-0100