H8SX1520 Datasheet, PDF (557/846 Pages) Renesas Technology Corp – 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series

Section 14 Synchronous Serial Communication Unit (SSU)
14.3.5 SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit
Bit Name
Initial Value
R/W
7
—
0
R/W
6
5
ORER
—
0
0
R/W
R/W
4
—
0
R/W
3
TEND
0
R/W
2
TDRE
1
R/W
1
RDRF
0
R/W
0
CE
0
R/W
Initial
Bit
Bit Name Value R/W
7

0

6
ORER
0
R/W
5, 4 
All 0
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While ORER
= 1, consecutive serial reception cannot be continued.
Serial transmission cannot be continued, either.
[Setting condition]
When one byte of the next reception is completed with
RDRF = 1
[Clearing condition]
When writing 0 after reading ORER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Mar. 14, 2006 Page 519 of 804
REJ09B0104-0300