H8SX1520 Datasheet, PDF (380/846 Pages) Renesas Technology Corp – 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series

Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.11 Conflict between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 9.54 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
Pφ
TCNT input
clock
TCNT
Counter clear
signal
TGF flag
TCFV flag
H'FFFF
Disabled
H'0000
Figure 9.54 Conflict between Overflow and Counter Clearing
9.9.12 Conflict between TCNT Write and Overflow/Underflow
If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write
cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 9.55 shows the operation timing when there is conflict between TCNT write and overflow.
TGR write cycle
T1
T2
Pφ
Address
TCNT address
Write
TCNT
H'FFFF
TCNT write data
M
TCFV flag
Figure 9.55 Conflict between TCNT Write and Overflow
Rev. 3.00 Mar. 14, 2006 Page 342 of 804
REJ09B0104-0300