H8SX1520 Datasheet, PDF (159/846 Pages) Renesas Technology Corp – 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series

Section 5 Interrupt Controller
Table 5.7 CPU Priority Control
Interrupt
Control Interrupt
Mode Priority
0
Default
2
IPR setting
Interrupt
Mask Bit
I = any
I=0
I=1
I2 to I0
Control Status
IPSETE in
CPUPCR CPUP2 to CPUP0
Updating of CPUP2
to CPUP0
0
B'111 to B'000
Enabled
1
B'000
Disabled
B'100
0
B'111 to B'000
Enabled
1
I2 to I0
Disabled
Table 5.8 shows an setting example of the priority control function over the DMAC and the
transfer request control state. Although the DMAC priority levels can be assigned for each
channel, table 5.8 gives a single channel description. Thus, transfer for each channel can be
performed independently by assigning the different priority levels.
Table 5.8 Example of Priority Control Function Setting and Control State
Interrupt Control CPUPCE in
Mode
CPUPCR
0
0
1
2
0
1
CPUP2 to
CPUP0
Any
B'000
B'100
B'100
B'100
B'000
Any
B'000
B'000
B'011
B'100
B'101
B'110
B'111
B'101
B'101
DMAP2 to
DMAP0
Any
B'000
B'000
B'011
B'101
B'101
Any
B'000
B'101
B'101
B'101
B'101
B'101
B'101
B'101
B'101
Transfer Request Control State
DMAC
Enabled
Enabled
Masked
Masked
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Masked
Masked
Enabled
Enabled
Rev. 3.00 Mar. 14, 2006 Page 121 of 804
REJ09B0104-0300