H8SX1520 Datasheet, PDF (11/846 Pages) Renesas Technology Corp – 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series

4.6 Interrupts.............................................................................................................................. 81
4.6.1 Interrupt Sources..................................................................................................... 81
4.6.2 Interrupt Exception Handling ................................................................................. 82
4.7 Instruction Exception Handling ........................................................................................... 83
4.7.1 Trap Instruction....................................................................................................... 83
4.7.2 Exception Handling by Illegal Instruction .............................................................. 84
4.8 Stack Status after Exception Handling................................................................................. 85
4.9 Usage Note........................................................................................................................... 86
Section 5 Interrupt Controller ..............................................................................87
5.1 Features................................................................................................................................ 87
5.2 Input/Output Pins ................................................................................................................. 88
5.3 Register Descriptions ........................................................................................................... 89
5.3.1 Interrupt Control Register (INTCR) ....................................................................... 89
5.3.2 CPU Priority Control Register (CPUPCR) ............................................................. 90
5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R
(IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR) ....................................... 92
5.3.4 IRQ Enable Register (IER) ..................................................................................... 94
5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL) .................................. 96
5.3.6 IRQ Status Register (ISR)..................................................................................... 101
5.3.7 Software Standby Release IRQ Enable Register (SSIER) .................................... 102
5.4 Interrupt Sources................................................................................................................ 103
5.4.1 External Interrupts ................................................................................................ 103
5.4.2 Internal Interrupts ................................................................................................. 104
5.5 Interrupt Exception Handling Vector Table....................................................................... 105
5.6 Interrupt Control Modes and Interrupt Operation .............................................................. 112
5.6.1 Interrupt Control Mode 0 ...................................................................................... 112
5.6.2 Interrupt Control Mode 2 ...................................................................................... 114
5.6.3 Interrupt Exception Handling Sequence ............................................................... 116
5.6.4 Interrupt Response Times ..................................................................................... 117
5.6.5 DMAC Activation by Interrupt............................................................................. 118
5.7 CPU Priority Control Function Over DMAC .................................................................... 120
5.8 Usage Notes ....................................................................................................................... 122
5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 122
5.8.2 Instructions that Disable Interrupts ....................................................................... 123
5.8.3 Times when Interrupts are Disabled ..................................................................... 123
5.8.4 Interrupts during Execution of EEPMOV Instruction........................................... 123
5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions.................... 123
5.8.6 Interrupt Flags of Peripheral Modules .................................................................. 124
Rev. 3.00 Mar. 14, 2006 Page xi of xxxviii