R01DS0140ED0100_FJ4_15 Datasheet, PDF (54/78 Pages) Renesas Technology Corp – 32-bit Single-Chip Microcontroller

Chapter 7
7.11 IIC timing
Table 7-6 Normal mode
Parameter
Symbol
Condition
SCL clock period
Bus free time (between stop condition
and start condition)
Start/Restart Hold time (New clock
pulse
is generated after this hold time as a
master.)
SCL clock low state hold time
SCL clock high state hold time
Setup time for start/restart condition
Data hold time
Data setup time
Rising transition time of SDA or SCL
Falling transition time of SDA or SCL
Setup time of stop condition
Bus capacitance
fCLK
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
CBUS compatible
IIC bus
Peripherals specification
Ratings
Unit
Min
Typ Max
0
100 kHz
4.7
-
- µs
4
-
- µs
4.7
-
- µs
4
-
- µs
4.7
-
- µs
5
-
- µs
0
-
- µs
250
-
- ns
-
- 1000 ns
-
- 300 ns
4
-
- µs
-
- 400 pF
R01DS0140ED0100
54
Data Sheet