R01DS0140ED0100_FJ4_15 Datasheet, PDF (41/78 Pages) Renesas Technology Corp – 32-bit Single-Chip Microcontroller

Chapter 7
7.7 CSI timing
Peripherals specification
7.7.1 Master modes
(1) CSIG timing
Table 7-2 CSIG timing (Master mode)
Parameter
Symbol
Condition
Ratings
Unit
Min
Typ Max
Macro Operation clock cycle
time
tKCYGn
20.8
-
- ns
CSIGnSC cycle time
tKCYMGn
100
-
- ns
CSIGnSC high level width tKWHMGn
0.5 · tKCYMGn-10 -
- ns
CSIGnSC low level width
tKWLMGn
0.5 · tKCYMGn-10 -
- ns
CSIGnSI setup time
(vs. CSIGnSC )
tSSIMGn CSIGnSC@PDSC=1
30
-
- ns
CSIGnSI setup time
(vs. CSIGnSC )
tSSIMGn CSIGnSC@PDSC=0
38
-
- ns
CSIGnSI hold time
(vs. CSIGnSC)
tHSIMGn
0
-
- ns
CSIGnSO output delay
(vs. CSIGnSC)
tDSOMGn
-
-
7 ns
CSIGnRYI setup time
(vs. CSIGnSC)
tSRYIGn
CSIGnCTL1.CSIGnSIT=x
CSIGnCTL1.CSIGnHSE=1
2 · tKCYGn+25
-
- ns
CSIGnRYI High level width tWRYIGn CSIGnCTL1.CSIGnHSE=1 tKCYGn- 5.0
-
- ns
Note n: Number of macro instances. Refer to the User Manual for the detailed
specification.
R01DS0140ED0100
41
Data Sheet