R01DS0140ED0100_FJ4_15 Datasheet, PDF (39/78 Pages) Renesas Technology Corp – 32-bit Single-Chip Microcontroller

Chapter 7
7.6 Timer timing
Peripherals specification
Table 7-1 Timer timing
Parameter
Symbol
Condition
Ratings
Unit
Min Typ Max
TAUAnI input High level
width
tTAIH n=0
a,b
-
-
ns
TAUAnI input Low level
width
tTAIL n=0
a,b
-
-
ns
TAUBnI input High level
width
tTBIH n=1
a_,b
-
-
ns
TAUBnI input Low level
width
tTBIL n=0
a,b
-
-
ns
TAUJnI input High level
width
tTJIH n=0,1
300
-
-
ns
TAUJnI input High level
width
tTJIH
4.7
-
-
µs
TAUJnI input High level
width
tTJIH
b
-
-
ns
TAUJnI input Low level
width
tTJIL n=0,1
300
-
-
ns
TAUJnI input Low level
width
tTJIL
4.7
-
-
µs
TAUJnI input Low level
width
tTJIL
b
-
-
ns
TAUAnO output cycle
tTACYK n=0
-
-
20 MHz
TAUBnO output cycle
tTBCYK n=1
-
-
20 MHz
TAUCnO output cycle
tTCCYK n=2-7
-
-
20 MHz
TAUJnO output cycle
tTJCYK n=0,1
-
-
20 MHz
TAPAnESO input High level
width
tWESH n=0
300
-
-
ns
TAPAnESO input Low level
width
tWESL n=0
300
-
-
ns
ENCAnTmIN high level
width
ENCAnTmIN low level width
tWENmH
tWENmL
n=0, m=A,B,Z
n=0, m=A,B,Z
a,b
-
a,b
-
-
ns
-
ns
ENCAnTINm high level
width
ENCAnTINm low level width
tWENmH
tWENmL
n=0, m=0-1
n=0, m=0-1
a,b
-
a,b
-
-
ns
-
ns
a) _{With digital noise filter enabled: 2, 3, 4 or 5 x Tsamp + 20 (Tsamp shows sampling period specified in Noise}
filter macro. More than 1 PCLK width of Timer macro must be kept regarding DNF pass through pulse width.
b) _{With digital noise filter disabled: 1xtSYNC+20 ( tSYNC: 1 PCLK of Timer macro)}
R01DS0140ED0100
39
Data Sheet