H8S68 Datasheet, PDF (530/1044 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip MicrocomputerH8S Family/H8S/2300 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin. After a match between TCNT and TGR, the compare match signal is not
generated until the (TIOC pin) TCNT input clock is generated.
Figure 10.32 shows output compare output timing.
φ
TCNT
input clock
TCNT
N
N+1
TGR
N
Compare
match signal
TIOC pin
Figure 10.32 Output Compare Output Timing
Input Capture Signal Timing: Figure 10.33 shows input capture signal timing.
φ
Input capture
input
Input capture
signal
TCNT
TGR
N
N+1
N+2
N
N+2
Figure 10.33 Input Capture Input Signal Timing
Rev.6.00 Mar. 18, 2009 Page 470 of 980
REJ09B0050-0600