H8S68 Datasheet, PDF (262/1044 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip MicrocomputerH8S Family/H8S/2300 Series

Section 6 Bus Controller (BSC)
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Normal space write Normal space read
DRAM/ space read
DRAM/ space write Normal space read
DRAM/ space read
ICIS2
0
1
0
1
0
1
0
1
ICIS1
—
—
—
—
—
—
—
—
ICIS0
—
—
—
—
—
—
—
—
DRMI
—
—
—
—
—
—
—
—
IDLC
—
0
1
—
0
1
—
0
1
—
0
1
Idle cycle
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/ space burst access. Figures 6.54 shows an
example of the timing for idle cycle insertion in the case of consecutive read and write accesses to
DRAM/continuous synchronous DRAM space.
Rev.6.00 Mar. 18, 2009 Page 202 of 980
REJ09B0050-0600