MC-10118B_15 Datasheet, PDF (52/66 Pages) Renesas Technology Corp – MULTIMEDIA PROCESSOR FOR MOBILE APPLICATIONS

MC-10118B
2.5.9 LCD interface
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
LCD_PXCLK cycle
tC
ʵ
30
ʵ
ʵ
ns
LCD_PXCLK high-level width
tWH
ʵ
12
ʵ
ʵ
ns
LCD_PXCLK low-level width
tWL
ʵ
12
ʵ
ʵ
ns
LCD_PXCLK rise time
tR
20 to 80%
ʵ
ʵ
5
ns
LCD_PXCLK fall time
tF
80 to 20%
ʵ
ʵ
5
ns
Data delay time
tD1
LCD_R[5:0], LCD_G[5:0],
0
LCD_B[5:0]
ʵ
10
ns
tD2
LCD_VSYNC, CD_HSYNC,
0
LCD_ENABLE
ʵ
10
ns
Remark The setting of the rise and fall timing for LCD_PXCLK is based on the valid edge set by the CLKPOL
value in the LCD control register (rising: CLKPOL = 0, falling: CLKPOL = 1).
Figure 2-16. LCD Interface Timing
tC
tWH
tWL
tR
tF
LCD_PXCLK
tD1
LCD_R[5:0]
LCD_G[5:0]
LCD_B[5:0]
tD2
LCD_ENABLE
LCD_HSYNC
LCD_VSYNC
50
Data Sheet R19DS0008EJ0700