MC-10118B_15 Datasheet, PDF (43/66 Pages) Renesas Technology Corp – MULTIMEDIA PROCESSOR FOR MOBILE APPLICATIONS

MC-10118B
2.5.3 Asynchronous bus (AB0) interface
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Asynchronous single
read access time
t201
Note
(1 + T0 + T1 + T2)
ʵ
(2 + T0 + T1 + T2) ns
 Tf  3
 Tf + 3
CSZ rise to ADVZ fall
ADVZ active width
t202
Note
t203 AB0_ADVZ = Low
Tf  3
Tf  3
ʵ
2Tf + 3
ns
ʵ
Tf + 3
ns
Lower ADD for ADMUX
t204
ʵ
hold time
T0  Tf  3
ʵ
T0  Tf + 3
ns
Delay time from ADVZ
rise to read signal output
t205 Falling edge of AB0_RDZ
T0  Tf  3
ʵ
T0  Tf + 3
ns
Read signal active width
t206 AB0_RDZ = Low
T1  Tf  3
ʵ
T1  Tf + 3
ns
Delay time from RDZ rise t207 Rising edge of AB0_RDZ
to CSZ fall output
T2  Tf  3
ʵ
T2  Tf + 3
ns
CS assert interval time
t208
ʵ
CSInt  Tf  3
ʵ
ʵ
ns
Asynchronous _RDATA
setup time
t209 Rising edge of AB0_RDZ
15
ʵ
ʵ
ns
Asynchronous _RDATA
hold time
t210 Rising edge of AB0_RDZ
0
ʵ
ʵ
ns
Delay time from address
t211
Falling edge of AB0_RDZ^Note
(1 + T0)  Tf  8
ʵ
determination to RDZ fall
ʵ
ns
Delay time from CSZ fall
t212 Falling edge of AB0_RDZ^Note
(1 + T0)  Tf  3
ʵ
to RDZ rise output
ʵ
ns
Asynchronous single
write access time
t220
Note
(1 + T0 + T1W +
ʵ
(2 + T0 + T1W +
ns
T2W)  Tf  3
T2W)  Tf + 3
Delay time from ADVZ
rise to write signal output
t221 Rising edge of AB0_WRZ
T0×Tf  3
ʵ
T0 Tf + 3
ns
Write signal active width
t222 AB0_WRZ = Low
T1W  Tf  3
ʵ
T1W  Tf + 3
ns
Delay time from WRZ
rise to CSZ fall output
t223 Rising edge of AB0_WRZ
T2W  Tf  3
ʵ
T2W  Tf + 3
ns
Asynchronous _WDATA
output hold time
t224 Rising edge of AB0_WRZ
T2W  Tf  8
ʵ
ʵ
ns
Delay time from address
t225 Falling edge of AB0_WRZ^Note (1 + T0)  Tf  8
ʵ
determination to WRZ
fall
ʵ
ns
Delay time from CSZ fall
t226 Falling edge of AB0_WRZ^Note (1 + T0)  Tf  3
ʵ
to WRZ fall output
ʵ
ns
Note The time from the CSB falling edge to the ADV falling edge (Tf) can be shortened by setting a register.
Remark
Tf = 1/4 of AB0_CLK. (When frequency ratio 1/4 is usually the time of the state (AB0_CLK:FLASH_CLK
= 2:1).
T0, T1, T2, CSInt: Values set to read the wait timing control register (AB0_CSxWAITCTRL)
T1W, T2W: Values set to write the wait timing control register (AB0_CSxWAITCTRL_W)
Data Sheet R19DS0008EJ0700
41