H8S-2268 Datasheet, PDF (51/725 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

20.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 510
20.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 511
20.5.3 Erase Block Register 1 (EBR1) ........................................................................... 512
20.5.4 Erase Block Register 2 (EBR2) ........................................................................... 513
20.5.5 RAM Emulation Register (RAMER)................................................................... 513
20.5.6 Flash Memory Power Control Register (FLPWCR) ............................................ 514
20.5.7 Serial Control Register X (SCRX)....................................................................... 515
20.6 On-Board Programming Modes ........................................................................................ 516
20.6.1 Boot Mode ........................................................................................................... 516
20.6.2 Programming/Erasing in User Program Mode..................................................... 519
20.7 Flash Memory Emulation in RAM.................................................................................... 520
20.8 Flash Memory Programming/Erasing ............................................................................... 522
20.8.1 Program/Program-Verify ..................................................................................... 523
20.8.2 Erase/Erase-Verify............................................................................................... 525
20.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 525
20.9 Program/Erase Protection.................................................................................................. 527
20.9.1 Hardware Protection ............................................................................................ 527
20.9.2 Software Protection.............................................................................................. 527
20.9.3 Error Protection.................................................................................................... 527
20.10 Interrupt Handling when Programming/Erasing Flash Memory....................................... 528
20.11 Programmer Mode ............................................................................................................ 528
20.12 Power-Down States for Flash Memory............................................................................. 530
20.13 Flash Memory Programming and Erasing Precautions ..................................................... 531
20.14 Note on Switching from F-ZTAT Version to Masked ROM Version............................... 536
Section 21 Clock Pulse Generator .................................................................................. 537
21.1 Register Descriptions ........................................................................................................ 538
21.1.1 System Clock Control Register (SCKCR) ........................................................... 538
21.1.2 Low-Power Control Register (LPWRCR) ........................................................... 539
21.2 System Clock Oscillator.................................................................................................... 541
21.2.1 Connecting a Crystal Resonator........................................................................... 541
21.2.2 External Clock Input ............................................................................................ 542
21.2.3 Notes on Switching External Clock ..................................................................... 544
21.3 Duty Adjustment Circuit ................................................................................................... 545
21.4 Medium-Speed Clock Divider .......................................................................................... 545
21.5 Bus Master Clock Selection Circuit .................................................................................. 545
21.6 Subclock Oscillator ........................................................................................................... 546
21.6.1 Connecting 32.768-kHz Crystal Resonator.......................................................... 546
21.6.2 Handling Pins when Subclock not Required........................................................ 547
21.7 Subclock Waveform Generation Circuit ........................................................................... 547
21.8 Usage Notes ...................................................................................................................... 547
Rev. 4.00 Mar 21, 2006 page li of lxviii