H8S-2268 Datasheet, PDF (196/725 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 8 Data Transfer Controller (DTC)
Table 8.3 Register Information in Normal Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register A
DTC transfer count register B
Abbreviation
SAR
DAR
CRA
CRB
Function
Designates source address
Designates destination address
Designates transfer count
Not used
SAR
Transfer
DAR
Figure 8.6 Memory Mapping in Normal Mode
8.5.2 Repeat Mode
In repeat mode, one operation transfers one byte or one word of data.
From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the
initial state of the transfer counter and the address register specified as the repeat area is restored,
and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and
therefore CPU interrupts cannot be requested when DISEL = 0.
Table 8.4 lists the register information in repeat mode. Figure 8.7 shows the memory mapping in
repeat mode.
Rev. 4.00 Mar 21, 2006 page 128 of 654
REJ09B0071-0400