H8S-2268 Datasheet, PDF (442/725 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 13 Serial Communication Interface (SCI)
Table 13.13 Interrupt Sources in Smart Card Interface Mode
Channel Name Interrupt Source
Interrupt Flag
DTC
Activation^*2
Priority^*1
0
ERI0 Receive Error, detection ORER, PER, ERS Not possible High
RXI0 Receive Data Full
RDRF
Possible
TXI0 Transmit Data Empty
TEND
Possible
1
ERI1 Receive Error, detection ORER, PER, ERS Not possible
RXI1 Receive Data Full
RDRF
Possible
TXI1 Transmit Data Empty
TEND
Possible
2
ERI2 Receive Error, detection ORER, PER, ERS Not possible
RXI2 Receive Data Full
RDRF
Possible
TXI2 Transmit Data Empty
TEND
Possible
Low
Notes: 1. Indicates the initial state immediately after a reset.
Priorities in channels can be changed by the interrupt controller. (H8S/2268 Group only)
2. Supported only by the H8S/2268 Group.
13.9 Usage Notes
13.9.1 Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 22, Power-Down Modes.
13.9.2 Break Detection and Processing (Asynchronous Mode Only)
When framing error (FER) detection is performed, a break can be detected by reading the RxD pin
value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and
possibly the PER flag. Note that as the SCI continues the receive operation after receiving a break,
even if the FER flag is cleared to 0, it will be set to 1 again.
13.9.3 Mark State and Break Detection (Asynchronous Mode Only)
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are
determined by DDR. This can be used to set the TxD pin to mark state (high level) or send a break
during serial data transmission. To maintain the communication line at mark state until TE is set to
1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an I/O port,
Rev. 4.00 Mar 21, 2006 page 374 of 654
REJ09B0071-0400