H8S-2268 Datasheet, PDF (145/725 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 5 Interrupt Controller
5.3.5 IRQ Status Register (ISR)
ISR indicates the status of IRQn (H8S/2268 Group: n = 5 to 3, 1, 0; H8S/2264 Group: n = 4, 3, 1,
0) interrupt requests.
Initial
Bit
Bit Name Value R/W Description
7, 6 
5
IRQ5F
All 0 R/W Reserved
The write value should always be 0.
0
R/(W)^*1 H8S/2268 Group:
IRQ5 Flag
Indicates the status of an IRQ5 interrupt request.
[Setting condition]
When the interrupt source selected by the ISCR registers
occurs
[Clearing conditions]
• Cleared by reading IRQ5F flag when IRQ5F = 1, then
writing 0 to IRQ5F flag
• When interrupt exception handling is executed when
low-level detection is set and IRQ5 input is high level
• When IRQ5 interrupt exception handling is executed
when falling, rising, or both-edge detection is set
• When the DTC is activated by an IRQ5 interrupt, and
the DISEL bit in MRB of the DTC is cleared to 0
H8S/2264 Group:
Reserved
The write value should always be 0.
Rev. 4.00 Mar 21, 2006 page 77 of 654
REJ09B0071-0400