NP80N04NUG Datasheet, PDF (5/12 Pages) Renesas Technology Corp – MOS FIELD EFFECT TRANSISTOR

NP80N04NUG, NP80N04PUG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS
VDS = 40 V, VGS = 0 V
Gate Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
Gate to Source Threshold Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
VGS(th)
| yfs |
RDS(on)
VDS = VGS, ID = 250 μA
VDS = 5 V, ID = 35 A
VGS = 10 V,
NP80N04NUG
ID = 40 A
NP80N04PUG
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage ^Note
Reverse Recovery Time
Reverse Recovery Charge
Note Pulsed test
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
VDS = 25 V,
VGS = 0 V,
f = 1 MHz
VDD = 20 V, ID = 40 A,
VGS = 10 V,
RG = 0 Ω
VDD = 32 V,
VGS = 10 V,
ID = 80 A
IF = 80 A, VGS = 0 V
IF = 80 A, VGS = 0 V,
di/dt = 100 A/μs
MIN.
2.0
25
TYP.
50
3.6
3.2
4900
480
310
32
23
65
11
90
21
31
0.92
40
44
MAX.
1
±100
4.0
4.8
4.5
7350
720
560
70
58
130
28
135
1.5
UNIT
μA
nA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
BVDSS
IAS
ID
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS ^90%
90%
10% 10%
tr td(off) tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
Data Sheet D19799EJ1V0DS
3