NP40N055EHE_15 Datasheet, PDF (5/12 Pages) Renesas Technology Corp – SWITCHING N-CHANNEL POWER MOS FET

NP40N055EHE, NP40N055KHE, NP40N055CHE, NP40N055DHE, NP40N055MHE, NP40N055NHE
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Drain to Source On-state Resistance
RDS(on)
VGS = 10 V, ID = 20 A
Gate to Source Threshold Voltage
VGS(th)
VDS = VGS, ID = 250 μA
Forward Transfer Admittance
| yfs |
VDS = 10 V, ID = 20 A
Drain Leakage Current
IDSS
VDS = 55 V, VGS = 0 V
Gate to Source Leakage Current
IGSS
VGS = ±20 V, VDS = 0 V
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Ciss
VDS = 25 V,
Coss
VGS = 0 V,
f = 1 MHz
Crss
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
td(on)
tr
td(off)
tf
ID = 20 A,
VGS = 10 V,
VDD = 28 V,
RG = 1 Ω
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
QG
ID = 40 A,
QGS
QGD
VDD = 44 V,
VGS = 10 V
Body Diode Forward Voltage
VF(S-D)
IF = 40 A, VGS = 0 V
Reverse Recovery Time
Reverse Recovery Charge
trr
IF = 40 A, VGS = 0 V,
Qrr
di/dt = 100 A/μs
MIN.
2.0
7
TYP. MAX.
18 23
3.0 4.0
14
10
±10
1070 1610
190 280
95 180
16 35
9.2 23
29 57
9.2 23
23 35
6
9
1.0
38
46
UNIT
mΩ
V
S
μA
μA
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
IAS
ID
VDD
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
RG
VGS
0
τ
τ = 1μs
Duty Cycle ≤ 1 %
RL
VDD
VGS
VGS
Wave Form
10 %
0
VDS
90 %
VDS
VDS
0
Wave Form
td(on)
90 %
VGS
90 %
10 % 10 %
tr td(off)
tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
Data Sheet D14092EJ6V0DS
3