HD74LS165A_05 Datasheet, PDF (5/8 Pages) Renesas Technology Corp – Parallel-Load 8-bit Shift Register

HD74LS165A
Waveforms 2
Clock Inhibit
Input
Clock
Input
1.3V
t_su
3V
(Disable while
clock is high)
0V
3V
1.3V 1.3V 1.3V
t_su
t_{w (clock)}
0V
3V
F and H
1.3V 1.3V
1.3V
1.3V
Inputs
(See Notes A and B)
t_su
t_{w (load)}
0V
t_{w (load)}
3V
Shift/
Load
1.3V 1.3V 1.3V 1.3V
0V
t_PHL
Output QH
t_PLH
1.3V
t_PHL
1.3V
t_PLH
1.3V
t_PHL
1.3V
t_PLH
1.3V
V_OH
V_OL
t_PLH
Output QH
t_PHL
1.3V 1.3V
t_PLH
1.3V
t_PHL
1.3V
t_PLH
1.3V
t_PHL
1.3V
V_OH
V_OL
Notes:
A. The remaining six data inputs and the serial input are low.
B. Prior to test, high-level data is loaded into H input.
C. The input pulse Generators have the following characteristics: PRR ≤ 1 MHz,
duty cycle ≤ 50%, Z_out ≈ 50 Ω, t_TLH ≤ 15 ns, t_THL ≤ 6 ns.
Rev.3.00, Jul.15.2005, page 5 of 7