HD74LS165A_05 Datasheet, PDF (2/8 Pages) Renesas Technology Corp – Parallel-Load 8-bit Shift Register

HD74LS165A
Function Table
Shift / Load
Clock
Inhibit
Inputs
Clock
Serial
Parallel
A…H
Internal outputs
Q_A
Q_B
Output
Q_H
L
X
X
X
a…h
a
b
h
H
L
↑
X
X
Q_A0
Q_B0
Q_H0
H
L
↑
H
X
H
Q_An
Q_Gn
H
L
↑
L
X
L
Q_An
Q_Gn
H
H
X
X
X
Q_A0
Q_B0
Q_H0
Notes: 1. H; high level, L; low level, X; irrelevant
2. ↑; transition from low to high level
3. a to h; the level of steady-state input at inputs A to H respectively
4. Q_A0 to Q_H0; the level of Q_A to Q_H, respectively, before the indicated steady-state input conditions were
established.
5. Q_An to Q_Gn; the level of Q_A to Q_G, respectively, before the most recent ↓ transition of the clock.
Block Diagram
A
B
C
D
E
F
G
H
Serial
Input
Shift /
Load
PR
PR
PR
PR
PR
PR
PR
PR
S QA S QB S QC S QD S QE S QF S QG S QH
QH
CK
CK
CK
CK
CK
CK
CK
CK
R QA R QB R QC R QD R QE R QF R QG R QH
QH
Clear Clear Clear Clear Clear Clear Clear Clear
Clock
Clock
Inhibit
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
V_CC
7
V
Input voltage
V_IN
7
V
Power dissipation
P_T
400
mW
Storage temperature
Tstg
–65 to +150
°C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Rev.3.00, Jul.15.2005, page 2 of 7