HD74LS165A_05 Datasheet, PDF (1/8 Pages) Renesas Technology Corp – Parallel-Load 8-bit Shift Register

HD74LS165A
Parallel-Load 8-bit Shift Register
REJ03D0449–0300
Rev.3.00
Jul.15.2005
The LS165A are 8-bit serial shift registers that shift the data in the direction of Q_A toward Q_H when clocked. Parallel-in
access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift /
load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. All inputs
are diode-clamped to minimize transmission-line effects, thereby simplifying system design.
Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit
function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift /
load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the
clock input is high. Parallel loading is inhibited as long as the shift / load input is high. Data at the parallel inputs are
loaded directly into the register on a high-to-low transition of the shift / load input independently of the levels of the
clock, clock inhibit, or serial inputs.
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74LS165AP
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
HD74LS165AFPEL SOP-16 pin (JEITA)
PRSP0016DH-B
FP
(FP-16DAV)
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
Pin Arrangement
Shift/
Load
1
Clock ²
E3
F4
Parallel
Inputs _{G 5}
H6
Output QH ⁷
GND 8
Shift/Load
CK ^Clock
Inhibit
E
D
F
C
G
B
H
A
QH
Serial
QH ^Input
16 V_CC
15
Clock
Inhibit
14 _D
13 _C
12 _B
Parallel
Inputs
11 _A
10
Serial
Input
9 _{Output QH}
(Top view)
Rev.3.00, Jul.15.2005, page 1 of 7