HD74HC597 Datasheet, PDF (5/10 Pages) Hitachi Semiconductor – 8-bit Latch/Shift Register

HD74HC597
Test Circuit
VCC
Input
Pulse Generator
Zout = 50 Ω
Input
Pulse Generator
Zout = 50 Ω
VCC
Output
SCLR
Q_H'
SLoad
RCK
A to H
SER
SCK
C_L = 50pF
Note : 1. C_L includes probe and jig capacitance.
Waveforms
• Waveform – 1 (RCK to QH')
tr
tf
90 %
V_CC
Input RCK
50 % 50 %
50 %
10 %
tw(H)
10 %
tw(L)
0V
t_PLH
t_PHL
90 %
90 %
V_OH
Output QH'
50 %
50 %
10 %
10 %
V_OL
t_TLH
t_THL
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, t_r ≤ 6 ns, t_f ≤ 6 ns
• Waveform – 2 (RCK to Q)
tr
tf
90 %
V_CC
Input SCK
50 % 50 %
50 %
10 %
tw(H)
10 %
tw(L)
0V
t_PLH
t_PHL
90 %
90 %
V_OH
Output QH'
50 %
50 %
10 %
10 %
V_OL
t_TLH
t_THL
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, t_r ≤ 6 ns, t_f ≤ 6 ns
Rev.2.00 Mar 30, 2006 page 5 of 9