HD74HC597 Datasheet, PDF (4/10 Pages) Hitachi Semiconductor – 8-bit Latch/Shift Register

HD74HC597
Switching Characteristics (C_L = 50 pF, Input t_r = t_f = 6 ns)
Item
Maximum clock
frequency
Propagation delay
time
Removal time
Setup time
Hold time
Pulse width
Output rise/fall
time
Input capacitance
Symbol VCC (V)
fmax
2.0
4.5
6.0
tPLH
2.0
tPHL
4.5
6.0
2.0
4.5
6.0
trem
2.0
4.5
6.0
tsu
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
th
2.0
4.5
6.0
2.0
4.5
6.0
tw
2.0
4.5
6.0
tTLH
2.0
tTHL
4.5
6.0
Cin
—
Ta = 25°C
Ta = –40 to +85°C
Min Typ Max Min Max Unit
Test Conditions
——
5
—
4 MHz
— — 27
—
21
— — 31
—
24
— — 175
—
— 14 35
—
220 ns SCK or SLoad or SCLR to QH’
44
— — 30
—
37
— — 210
—
265 ns RCK to QH’
— 17 42
—
53
— — 36
—
45
100 —
—
125
— ns
20 —
–
25
—
17 — —
21
—
100 —
—
125
— ns RCK to SCK
20 — —
25
—
17 — —
21
—
100 —
—
125
— ns SER to SCK
20
1
—
25
—
17 — —
21
—
100 —
—
125
— ns Data to RCK
20
0
—
25
—
17 — —
21
—
5 ——
5
5 ——
5
—
ns SCK to SA
—
5 ——
5
—
5 ——
5
— ns LCK to Data
5 ——
5
—
5 ——
5
—
80 —
—
100
— ns
16
7
—
20
—
14 — —
17
—
— — 75
—
95 ns
— 4 15
—
19
— — 13
—
16
— 5 10
—
10 pF
Rev.2.00 Mar 30, 2006 page 4 of 9