HD151011 Datasheet, PDF (5/14 Pages) Hitachi Semiconductor – Dual BCD Programmable Counter with Synchronous Preset Enable

HD151011
Switching Characteristics (C_L = 50 pF, t_r = t_f = 6 ns)
Ta =
Sym-
Ta = 25°C
–40 to 85°C
Item
Maximum clock
frequency
bol
f_max
V_CC Min Typ Max Min Max Unit
2.0 — — 4
—3
MHz
4.5 — 36 20 — 16
Test Conditions
6.0 — — 24 — 19
Output rise/fall time
t_TLH
2.0 — 30 75 — 95 ns
t_THL
4.5 — 8
15 — 19
6.0 — 7
13 — 16
Propagation delay time t_PLH
t_PHL
2.0 — — 250 — 318 ns CLK or CLK to CO
4.5 — 30 50 — 63
6.0 — — 45 — 53
t_PLH
2.0 — — 300 — 380
t_PHL
4.5 — 35 60 — 75
6.0 — — 53 — 65
CLK or CLK to Q
t_PLH
2.0 — — 150 — 185
t_PHL
4.5 — 18 30 — 38
6.0 — — 25 — 32
PR or CLK to Q
Pulse width
t_w
(CLK, CLK, PR, CLR)
2.0 80 — — 100 — ns
4.5 16 — — 20 —
6.0 14 — — 17 —
Setup time
(Jn - CLK, CLK)
t_s
2.0 100 — — 125 — ns
4.5 20 — — 25 —
(SPE, CLK, CLK)
6.0 17 — — 21 —
Hold time
(Jn - CLK, CLK)
t_h
2.0 15 — — 15 — ns
4.5 10 — — 10 —
(SPE, CLK, CLK)
6.0 5
——5
—
Input capacitance
Power dissipation
capacitance*¹
C_IN
——5
10 — 10 pF
C_PD
— — 48 — — — pF
Note: 1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test
circuit). The average operating current without load is calculated according to the expression below.
I_CC (opr) = C_PD • V_CC • f_IN + I_CC
Rev.2.00, Jul.16.2004, page 5 of 13