HD151011 Datasheet, PDF (3/14 Pages) Hitachi Semiconductor – Dual BCD Programmable Counter with Synchronous Preset Enable

HD151011
Pin Description
Pin Name
Input pins
J0 to J7
C/T
CLK, CLK
Output pins
SPE
PR
CLR
CO
Q
Pin Description
Count data input for option
Level change input for CLK, CLK (CMOS level or TTL level)
Clock inputs
CLK : Rise edge trigger
CLK : Fall edge trigger
Preset input for Jn data
Preset input for D-type Flip Flop (Initialize “L” at Q output)
Clear input for D-type Flip Flop (Initialize “H” at Q output)
Output for BCD decimal counter
Output for D-type Flip Flop
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
Input/output voltage
V_CC, GND current
Output current/pin
Power dissipation
Storage temperature
V_CC
V_IN/V_OUT
I_CC, I_GND
I_OUT
P_T
Tstg
–0.5 to 7.0
V
–0.5 to V_CC +0.5
V
±50
mA
±25
mA
757
mW
–65 to 150
°C
Input diode current
I_IK
±20
mA
Output diode current
I_OK
±20
mA
Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two
of which may be realized at the same time.
2. All voltage values except for differential input voltage are with respect to network ground terminal.
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Supply voltage
Input/output voltage
Operating temperature
V_CC
2
—
V_IN/_OUT
0
—
Topr
–40
—
6
V
V_CC
V
+85
°C
Input rise/fall time*¹
V_CC = 2.5 V
t_r, t_f
0
—
V_CC = 4.5 V
0
—
V_CC = 5.5 V
0
—
Note: 1. This item guarantees maximum limit when one input switches.
1000
ns
500
400
Unit
Logic Diagram
J0
J1
J2
J3
J4
J5
J6
J7
J0
CLK
J1
J2
J3
J4
J5
J6
CO
J7
SPE
PR
D
Q
CK
Q
CLR
C/T
CLK
CLK
CO
PR
Q
SPE
CLR
Rev.2.00, Jul.16.2004, page 3 of 13