HD151011 Datasheet, PDF (2/14 Pages) Hitachi Semiconductor – Dual BCD Programmable Counter with Synchronous Preset Enable

HD151011
Function Table
Control Inputs
CLR PR SPE C/T
Mode
Operation Description
H
H
H
X
Generally count
Down count at the rise edge of clock (CLK)
Down count at the fall edge of clock (CLK)
X
X
L
X
Synchronous preset Jn data is preset at the rise of clock (CLK), the fall of clock
(CLK)
—
—
—
H
—
Clock inputs (CLK, CLK) is CMOS level
—
—
—
L
—
Clock inputs (CLK, CLK) is TTL level
L
H
—
—
Initialize of Q output Initialize of Q = “L”
H
L
—
—
Initialize of Q output Initialize of Q = “H”
Note: 1. Synchronous preset (SPE) input can set max 99 down counts.
2. When the count value is 0, the next clock pulse presets the data to invert the output.
3. CLR and PR inputs initialize output state.
4. Clock inputs (CLK, CLK) is selectable CMOS level (V_CC = 2.0 to 6.0 V) and TTL level (V_CC = 4.5 to 5.5V) (Jn,
C/T, PR, CLR and SPE inputs are CMOS level)
Don't set data exceeding 99 to Jn. (J0 : LSB, J7 : MSB)
H : High level
L : Low level
X : Immaterial
— : Irrespective of condition
Pin Arrangement
CO 1
J0 2
J1 3
J2 4
J3 5
J4 6
J5 7
J6 ₈
J7 9
GND 10
20 VCC
19 (Test 1) ^*
18 (Test 2) ^*
17 C / T
16 CLK
15 CLK
14 Q
13 PR
12 SPE
11 CLR
(Top view)
Rev.2.00, Jul.16.2004, page 2 of 13