H8S2268_09 Datasheet, PDF (492/712 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 14 I²C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
I²C bus interface
(Master transmit mode)
Other device
(Master transmit mode)
I²C bus interface
(Slave receive mode)
• Arbitration is lost
• The AL flag in ICSR is set to 1
S
SLA R/W A
DATA1
Transmit data match
Transmit timing match
Transmit data does not match
S
SLA
R/W A
DATA2
A
DATA3
A
S
SLA
R/W A
• Receive address is ignored
SLA
R/W A
• Automatically transferred to slave
receive mode
• Receive data is recognized as an
address
• When the receive data matches to
the address set in the SAR or SARX
register, the I²C bus interface operates
as a slave device.
Data contention
DATA4
A
Figure 14.27 Diagram of Erroneous Operation when Arbitration Is Lost
Though it is prohibited in the normal I²C protocol, the same problem may occur when the MST
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to
1 according to the order below.
(1) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
(2) Set the MST bit to 1.
(3) To confirm that the bus was not entered to the busy state while the MST bit is being set,
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
16. Notes on Wait Operation in Master Mode
When attempting to use the wait function in master mode, if the interrupt flag IRIC bit is
cleared from 1 to 0 between the falling edges of the seventh and eighth clock pulses, the LSI
may fail to enter wait status after the falling edge of the eighth clock pulse and instead output
the ninth clock pulse continuously.
When using the wait function, keep the following points in mind with regard to clearing the
IRIC flag.
Ensure that the IRIC flag is set to 1 at the rising edge of the ninth clock pulse and cleared to 0
before the rising edge of the seventh clock pulse (when the counter value in BC2 to BC0 is 2
or higher).
Rev. 5.00 Sep. 01, 2009 Page 440 of 656
REJ09B0071-0500