H8S2268_09 Datasheet, PDF (302/712 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is inhibited. A compare match does not occur even if the previous
value is written.
Figure 10.48 shows the timing in this case.
φ
Address
TGR write cycle
T1
T2
TGR address
Write signal
Compare
match signal
TCNT
Inhibited
N
N+1
TGR
N
M
TGR write data
Figure 10.48 Contention between TGR Write and Compare Match
Rev. 5.00 Sep. 01, 2009 Page 250 of 656
REJ09B0071-0500