H8S2268_09 Datasheet, PDF (418/712 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 13 Serial Communication Interface (SCI)
13.7.4 Receive Data Sampling Timing and Reception Margin
In Smart Card interface mode an internal clock generated by the on-chip baud rate generator can
only be used as a transmission/reception clock. In this mode, the SCI operates on a basic clock
with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed to 16 times in normal
asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the
falling edge of the start bit using the basic clock, and performs internal synchronization. As shown
in figure 13.28, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th
pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given
by the following formula.
M = | (0.5 – ¹ ) – (L – 0.5) F – ^{| D – 0.5 |} (1 + F) | × 100%
2N
N
Where
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
Internal
basic clock
372 clocks
186 clocks
0 185
371 0
185
371 0
Receive data
Start bit
D0
D1
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 13.28 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Transfer Rate)
Rev. 5.00 Sep. 01, 2009 Page 366 of 656
REJ09B0071-0500