H8S2268_09 Datasheet, PDF (298/712 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
φ
TCNT
input clock
TCNT
(underflow)
Underflow
signal
TCFU flag
H'0000
H'FFFF
TCIU interrupt
Figure 10.42 TCIU Interrupt Setting Timing (H8S/2268 Group Only)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated in the H8S/2268 Group, the flag is cleared automatically.
Figure 10.43 shows the timing for status flag clearing by the CPU, and figure 10.44 shows the
timing for status flag clearing by the DTC.
TSR write cycle
T1
T2
φ
Address
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 10.43 Timing for Status Flag Clearing by CPU
Rev. 5.00 Sep. 01, 2009 Page 246 of 656
REJ09B0071-0500