H8S2215 Datasheet, PDF (420/878 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 11 8-Bit Timers (TMR)
11.8.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the write
takes priority and the counter is not incremented. Figure 11.11 shows this operation.
TCNT write cycle by CPU
T₁
T₂
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 11.11 Contention between TCNT Write and Increment
Rev.7.00 Mar. 27, 2007 Page 362 of 816
REJ09B0140-0700