H8S2215 Datasheet, PDF (145/878 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 5 Interrupt Controller
5.3.1
Interrupt Priority Registers A to G, I to K, M (IPRA to IPRG, IPRI to IPRK,
IPRM)
The IPR registers set priorities (levels 7 to 0) for interrupts other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a
value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of
the corresponding interrupt.
Bit Bit Name Initial Value R/W Description
7
—
0
—
Reserved
These bits are always read as 0 and cannot be
modified.
6
IPR6
1
R/W Sets the priority of the corresponding interrupt source.
5
IPR5
1
R/W 000: Priority level 0 (Lowest)
4
IPR4
1
R/W 001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
3
—
0
—
Reserved
These bits are always read as 0 and cannot be
modified.
2
IPR2
1
R/W Sets the priority of the corresponding interrupt source.
1
IPR1
1
R/W 000: Priority level 0 (Lowest)
0
IPR0
1
R/W 001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
Rev.7.00 Mar. 27, 2007 Page 87 of 816
REJ09B0140-0700