H8S2144B Datasheet, PDF (408/546 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 16 ROM
16.9 Programming/Eraseing Protection
There are three kinds of flash memory programming/erasing protection: hardware protection,
software protection, and error protection.
16.9.1 Hardware Protection
Hardware protection is a state in which programming/erasing of flash memory is forcibly disabled
or aborted by a reset (including WDT overflow reset), or a transition to hardware standby mode,
software standby mode, sub-active mode, sub-sleep mode or watch mode. Flash memory control
registers 1 and 2 (FLMCR1 and FLMCR2) and erase block registers 1 and 2 (EBR1 and EBR2)
are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held
low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the
RES pin low for the RES pulse width specified in the AC Characteristics section.
16.9.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1 to 0. When software protection is in effect, setting the P or E
bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase
block registers 1 and 2 (EBR1 and EBR2), erase protection can be set for individual blocks. When
EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.
16.9.3 Error Protection
In error protection, an error is detected when the CPU’s runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the programming/erasing
algorithm, and the programming/erasing operation is aborted. Aborting the programming/erasing
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of is read during programming/erasing (including vector read and
instruction fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction is executed (transits to software standby mode, sleep mode, sub-
active mode, sub-sleep mode, or watch mode) during programming/erasing
• When the bus ownership is released during programming/erasing
Rev. 1.00 Jun.24, 2005 Page 376 of 510
REJ09B0241-0100