H8S2144B Datasheet, PDF (152/546 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 6 Bus Controller (BSC)
8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space.
When an 8-bit access space is accessed, the upper byte (D15 to D8) of the data bus is used in the
H8S/2144B. Wait cycles can be inserted.
φ
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
D15 to D8
Read ^{(D7 to D0 in H8S/2134B)}
D7 to D0
(Invalid in H8S/2134B)
Write
HWR
D15 to D8
(D7 to D0 in H8S/2134B)
Bus cycle
T₁
T₂
T₃
Valid
Invalid
Valid
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space
Rev. 1.00 Jun.24, 2005 Page 120 of 510
REJ09B0241-0100